基于线段投影的ADMM-LP译码算法硬件实现

Hardware Implementation of ADMM-LP Decoding Algorithm Based on Line Segment Projection Algorithm

奇偶校验多胞体投影是交替方向乘子法(alternating direction method of multipliers, ADMM)译码算法中最为复杂的部分,复杂的投影计算使得ADMM译码算法复杂度较高且无高效的硬件实现方案。使用线段投影算法(line segment projection algorithm, LSA)计算校验多胞体投影可以省去复杂的排序和迭代操作,仅需进行简单的加减与比较运算,十分适合硬件实现。首先针对硬件实现对线段投影算法进行简化,并设计了完整的ADMM译码硬件实现方案,在FPGA (field programmable logic gate array)中搭建了完整译码平台进行实验。实验表明:相较于已有的译码器,本文实现的ADMM-LSA译码器误码率性能基本一致,译码速度提高了30.6%,且在硬件资源消耗上有大幅减少,其中LUT (look up table)资源使用量减少了40.3%,(flip flop, FF)资源减少67.6%,(digital signal processing, DSP)资源减少54.5%。

Parity check polytope projection is the most complex part of alternating direction method of multipliers(ADMM)decoding.Due to the complex calculation of check polytope projection,there is no efficient hardware implementation scheme for ADMM decoding algorithm.Using the line segment projection algorithm(LSA)to calculate the check polytope projection can save the complicated sorting and iterative operations,and only need to perform simple addition,subtraction and comparison operations,which is very suitable for hardware implementation.Firstly,the line segment projection algorithm was simplified for hardware implementation and a complete hardware implementation scheme of ADMM decoding was designed.Then,the complete decoding platform was built on FPGA(field programmable logic gate array)for the experiments.Experiments show that compared with the existing decoder,the frame error rate performance of the ADMM-LSA decoder implemented is basically the same,the decoding speed is increased by 30.6%.And there is a significant reduction in hardware resource consumption,among which the LUT(look up table)resource usage can be saved by 40.3%,FF(flip flop)resource can be saved by 67.6%,DSP(digital signal processing)resource can be saved by 54.5%.