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非默认规则线技术下基于多策略的时延驱动层分配算法

Multi-Strategy Delay-Driven Layer Assignment for Non-Default-Rule Wiring Techniques
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摘要 层分配作为超大规模集成电路物理设计中的关键环节,在决定布线方案的时延起到非常重要作用.为了优化集成电路的时延性能,现有的层分配工作通常注重优化互连时延和通孔数量,但要么未考虑到对线网中时序关键段的分配问题,要么对线网段的时序关键性的表示不够合理,最终使得算法的时延优化不够理想.为此,本文提出一种非默认规则线技术下基于多策略的时延驱动层分配算法,主要包含4种关键策略:(1)提出轨道数感知的层选择策略,增强层分配器为线网段选择合适布线层的能力;(2)提出多指标驱动的初始线网排序策略,综合考虑线长、信号接收器数和可布线轨道资源等多个指标为线网确定层分配优先级,从而获得高质量的初始层分配结果;(3)提出线网段调整策略,通过重绕线网,将时序关键段调整至上层布线层,优化线网时延;(4)提出线网段时延优化策略,对存在溢出线网进行拆线重绕,从而可同时优化时延和溢出数.实验结果表明,本文提出的算法相比于现有的层分配算法能够在时延和通孔数两个指标上均取得最佳,并且保证不产生溢出. As a key step in the physical design of very large scale integration,layer assignment plays a very important role in determining the delay of routing solution.At the same time,with the continuous progress of technical nodes,the density of the nets is increasing.Interconnect delay is an important factor to evaluate the performance of the routing results.In order to optimize the delay in integrated circuits,the existing layer assignment algorithms usually focus on minimizing interconnect delay and via count.However,the existing work either does not consider the assignment of the timing-critical segments in nets,or the time critical representation of wire segments is not reasonable,which ultimately makes the delay optimization not ideal.For this reason,this paper proposes a multi-strategy delay-driven layer assignment for non-default-rule wire technique,which mainly includes the following key strategies:(1)In order to avoid the local optimization of the nets,a track number aware layer selection strategy is proposed.This strategy enhances the ability of layer assigner to select suitable routing layers for wire segments so that it allows the layer with the largest number of remaining tracks to be given priority in the layer assignment to avoid overflow in the routing layer.(2)A multi-index driven initial net sorting strategy is proposed.This strategy fully considers the characteristics of different nets to determine the priority of nets,and comprehensively considers multiple indicators such as the wirelength,the number of sink points,and the resource of routing tracks to determine the priority of layer assignment for the network,so that the high-quality initial layer assignment results is obtained.(3)In order to further optimize the delay,a wire segment adjusting strategy is proposed.This strategy is adopted to optimize the delay of nets by re-assigning nets and assigning the timingcritical segments on upper layers.(4)A wire segment delay optimization strategy is proposed to optimize the delay of nets while eliminating overflow by ripping up and re-assigning the nets which have overflow.This strategy not only makes the final routing result not overflow,but also makes it have better delay.And the proposed algorithm is mainly composed of three stages.First,a better initial layer assignment result is obtained through the multi-index driven initial net sorting strategy.Then,the proposed algorithm adjusts the routing layer of the timing-critical segments through the wire segment adjusting strategy,and then eliminates the overflow while optimizing delay through the wire segment delay optimization strategy.Finally,under the condition of satisfying the congestion constraint,the proposed algorithm rips up and re-assigns the nets to select a better layer assignment result.In each stage,the track number aware layer selection strategy is used in the single net layer assignment so that the track resources of upper layers can be fully utilized.This paper uses the DAC12 benchmarks to verify the effectiveness of the related strategies and the proposed algorithm.The experimental results show that the proposed algorithm can achieve the best performance in both delay and via count among the existing algorithms without overflow.
作者 刘耿耿 鲍晨鹏 王鑫 郭文忠 陈国龙 LIU Geng-Geng;BAO Chen-Peng;WANG Xin;GUO Wen-Zhong;CHEN Guo-Long(College of Computer and Data Science,Fuzhou University,Fuzhou 350116;State Key Laboratory of Computer System and Architecture,Beijing 100190;College of Intelligence and Computing,Tianjin University,Tianjin 300350;Tianjin Key Laboratory of Cognitive Computing and Application,Tianjin 300350)
出处 《计算机学报》 EI CAS CSCD 北大核心 2023年第4期743-760,共18页 Chinese Journal of Computers
基金 国家自然科学基金(61877010) 计算机体系结构国家重点实验室开放课题(CARCHB202014)资助.
关键词 超大规模集成电路 层分配 时延 通孔 时序关键段 very large scale integration layer assignment delay via timing-critical segments
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