1200 V SiC MOSFET重复非钳位感性开关测试的退化机制研究

Degradation mechanism of 1200 V SiC MOSFET with repetitive unclamped-inductive-switching

为了研究1200 V SiC MOSFET在重复非钳位感性开关(Unclamped-Inductive-Switching,UIS)应力下的电学参数退化机制,基于自行搭建的UIS实验平台以及Sentaurus仿真设计工具,首先深入分析了重复UIS测试后器件静态参数与动态参数的退化;接着基于FN隧穿公式对栅极漏电流数据进行拟合,得到随着UIS测试次数增加SiC/SiO2界面的势垒高度从2.52 eV逐渐降低到2.06 eV;最后解释了SiC MOSFET在重复UIS测试后的电流输运过程。结果表明,在重复雪崩应力的作用下,大量的正电荷注入至结型场效应管区域上方的栅极氧化层中,影响了该区域的电场分布以及耗尽层厚度,导致被测器件(Device Under Test,DUT)的导通电阻、漏源泄漏电流、电容特性等电学参数呈现出不同程度的退化,并且氧化物中的正电荷的积累也使电子隧穿通过栅介质的电流得到了抬升。

To investigate the electrical parameter degradation mechanisms of 1200 V SiC MOSFET under repetitive unclamped-inductive-switching(UIS)stresses,the static and dynamic parameters degradations of the device under repetitive avalanche stress were investigated in depth based on self-built UIS experimental platform and Sentaurus technology computer aided design tools.Then the curve of the gate leakage current was fitted by FN tunneling,and it turned out that the barrier height of SiC/SiO2 decreased from 2.52 eV to 2.06 eV gradually with the increase of UIS cycles.The results show that under repetitive UIS stresses,a large amount of the positive charge is trapped into the gate oxide above the junction field-effect transistor region,the electric field distribution and the thickness of the depletion region were affected,leading to the electrical parameter degradation of the device-under-test(DUT),such as on-resistance,drain-source leakage current and capacitance characteristics.Meanwhile,the accumulation of the positive charge in the oxide increases the electron tunneling current through the gate dielectric.