一种高共模抑制比轨到轨全差分运算放大器

A rail-to-rail fully differential operational amplifier with high common-mode rejection ratio

针对传统全差分运算放大器电路存在输入输出摆幅小和共模抑制比低的问题,提出了一种高共模抑制比轨到轨全差分运算放大器电路。电路的输入级采用基于电流补偿技术的互补差分输入对,实现较大的输入信号摆幅;中间级采用折叠式共源共栅结构,获得较大的增益和输出摆幅;输出级采用共模反馈环路控制的A类输出结构,同时对共模反馈环路进行密勒补偿,提高电路的共模抑制比和环路稳定性。提出的全差分运算放大器电路基于中芯国际(SMIC)0.13μm CMOS工艺设计,结果表明,该电路在3.3 V供电电压下,负载电容为5 pF时,可实现轨到轨的输入输出信号摆幅;当输入共模电平为1.65 V时,直流增益为108.9 dB,相位裕度为77.5°,单位增益带宽为12.71 MHz;共模反馈环路增益为97.7 dB,相位裕度为71.3°;共模抑制比为237.7 dB,电源抑制比为209.6 dB,等效输入参考噪声为37.9 nV/Hz^(1/2)@100 kHz。

To address the problems of small input and output swing and low common-mode rejection ratio of conventional fully differential operational amplifier circuits,a rail-to-rail fully differential operational amplifier circuit was proposed with high common-mode rejection ratio.Complementary differential input pairs based on current compensation technology was adopted by the input stage to achieve large input signal swing.The folded cascade structure was adopted at the middle stage to obtain large gain and output swing.Class-A output structure controlled by common mode feedback loop was adopted by the output stage,and Miller compensation was applied in the common mode feedback loop to improve the common mode rejection ratio and loop stability of the circuit.The proposed circuit was designed using SMIC 0.13μm CMOS process.Simulation results show that the circuit can achieve rail-to-rail input and output signal swing at 3.3 V supply voltage with a load capacitance of 5 pF.When the input common-mode level is 1.65 V,the DC gain and phase margin are 108.9 dB and 77.5°with the unit gain bandwidth of 12.71 MHz,common mode feedback loop gain of 97.7 dB,phase margin of 71.3°,common mode rejection ratio of 237.7 dB,power supply rejection ratio of 209.6 dB,and equivalent input reference noise of 37.9 nV/Hz^(1/2)@100 kHz.