摘要
阐述UltraScale FPGA高速以太网接口的硬件设计要求,高速以太网接口的硬件设计,根据10G以太网信号完整性要求进行高速信号仿真。探讨信号完整性仿真,优化高速信号PCB设计。
This paper describes the hardware design requirements of the UltraScale FPGA highspeed Ethernet interface, the hardware design of the high-speed Ethernet interface, and the highspeed signal simulation according to the 10G Ethernet signal integrity requirements. It discusses signal integrity simulation and optimizes high-speed signal PCB design.
作者
崔钟允
姬利
CUI Zhongyun;JI Li(AViC Xi'an Institute of Aeronautical Computing Technology,Shaanxi 710068,China)
出处
《电子技术（上海）》
2023年第2期34-36,共3页
Electronic Technology
关键词
高速接口
FPGA
通信网络
high-speed interface
FPGA
communication network
