基于FPGA高速浮点控制算法的设计架构与应用

Design architecture and application of high-speed floating point control algorithm based on FPGA

为满足控制系统对高速处理、高精度运算的需求,提出一种基于现场可编程门阵列(FPGA)的高速浮点控制算法的设计架构。利用System Generator工具设计浮点控制算法并生成其IP核;VHDL编写模/数(A/D)、数/模(D/A)转换芯片的驱动逻辑;而后顶层中按照时序逻辑关系连接各模块;最终在FPGA中实现硬件控制。将算法设计架构应用在快速反射镜的闭环控制中,实验结果表明:单精度浮点格式的PID算法执行时间为2~3个采样周期,整个控制算法最快执行仅需10个时钟周期,闭环控制周期为6.55μs。实验验证了提出的算法设计架构具有可行性;该架构设计的控制器具有高速的处理性能和高精度的控制效果。

In order to meet the requirement of control system for high-speed processing,high-precision computing,a high-speed floating point control algorithm based on field programmable gate array(FPGA)is proposed.The System Generator tool is used to design the floating-point control algorithm and its IP core is generated.VHDL is used to driver logic of the analog-to-digital(A/D),digital-to-analog(D/A)conversion chip.Then,the top layer connects each modules according to the sequential logic relationship.Finally,hardware control is realized in FPGA.The algorithm design framework is applied to the closed-loop control of fast reflector.The experimental results show that the single-precision floating point PID algorithm takes 2~3 sampling cycles.The fastest time to execute the whole control algorithm is 10 clock cycles,the closed-loop control period is 6.55μs.The experimental results show that design framework of the proposed algorithm is feasible.The controller designed with this architecture has high speed processing performance and high precision control effect.