基于65 nm CMOS工艺的小型化高增益低噪声放大器设计

Design of Miniaturized High-Gain Low Noise Amplifier Based on 65 nm CMOS Process

基于65 nm互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)工艺研制了一款用于X波段的小型化高增益低噪声放大器(Low Noise Amplifier,LNA).通过研究晶体管尺寸和偏置电压对噪声系数和增益性能的影响,确定了低噪声高增益情况下晶体管尺寸和偏置电压的取值.针对LNA的输入、输出和级间匹配,采用变压器匹配网络,使得LNA尺寸缩小至0.33 mm×0.73 mm,同时提高了电路的隔离度.在变压器中嵌入并联电容,降低了变压器的耦合系数.基于差分共源拓扑结构,引入中和电容技术,有效地抑制了晶体管栅-漏间寄生电容引起的米勒效应,提高了LNA的增益和稳定性.测试结果表明,在1 V电源电压下,该LNA的带内最大增益为22.9 dB,最小噪声系数为2.8 dB,功耗为49 mW.在射频收发系统中,本款LNA具有良好的应用前景.

An X-band miniaturized high-gain low noise amplifier(LNA)is developed based on 65 nm Complementa⁃ry Metal Oxide Semiconductor(CMOS)process.By studying the influence of transistor size and bias voltage on noise fig⁃ure and gain performance,the transistor size and bias voltage under low noise and high gain condition are determined.The transformer matching network is adopted for the input,output and inter-stage matching of LNA,which reduces the LNA size to 0.33 mm×0.73 mm and improves the circuit isolation.By embedding shunt capacitance in the transformer,the cou⁃pling coefficient of the transformer is reduced.Furthermore,based on the differential common source(CS)topology,the neutralization capacitance technology is introduced to effectively suppress the Miller effect caused by the parasitic capaci⁃tance between the gate and drain of the transistor,and improve the gain and stability of the LNA.The test results show that the maximum in-band gain of the LNA is 22.9 dB,the minimum noise figure is 2.8 dB and the power consumption is 49 mW at 1 V supply voltage.In the RF transmitter and receiver system,this LNA has a good application prospect.