一种10bit低功耗SAR ADC设计

A 10bit Low Power SAR ADC Design

设计了一种10 bit、1 MS/s低功耗SAR ADC,在传统SAR ADC的基础上改进了电容阵列的算法,加入了高位隔离开关,改进了栅压自举开关的电路。采用SMIC 55nm CMOS工艺实现了电路,工作电压为1.2 V,在采样频率为1 MHz,输入信号频率为16.601 kHz时,有效位数(Effective Number of Bits,ENOB)为9.82位,信噪比(Signal to Interference plus Noise Radio,SNDR)为60.91 dB,无杂散动态范围(Spurious Free Dynamic Range,SFDR)为72.92 dB,得到平均功耗为1.38μW,优值为1.34 fJ/convertion-step。

In this paper,a 10bit,1MS/s low-power SAR ADC is designed,which improves the algorithm of capacitor array,adds high-position isolation switch,and improves the circuit of gate-voltage bootstrap switch.The circuit is implemented in SMIC 55 nm CMOS process.The operating voltage is 1.2 V.When the sampling frequency is 1 MHz and the input signal frequency is 16.601 kHz,the Effective Number of Bits(ENOB)is 9.82 bit,SNR is 60.91 dB,and SFDR is 72.92 dB.The average power consumption is 1.38μW,the optimal value is 1.34 fJ/convertion-step.