视频阵列处理器HEVC去块滤波算法动态重构实现

Implementation of dynamic reconstruction of HEVC deblocking filtering algorithm for video array processor

去块滤波算法是高效视频编码标准(high-efficiency video coding,HEVC)的重要组成部分,专用硬件实现的去块滤波电路结构难以满足不断革新的算法需求,可重构计算兼具计算高效性和编程灵活性成为研究热点。基于指令流与数据流混合驱动可重构视频阵列处理器(reconfigurable video array processor,RVAP),提出一种可重构的HEVC编码去块滤波电路的并行化实现方法,依据数据流图分析实现去块滤波算法的最大化并行,提高计算效率;通过强/弱滤波方式的灵活切换,提高计算资源利用率。实验结果表明,所提方法在满足算法灵活切换和计算速度要求的同时,硬件资源减少了47.6%,时钟频率达167 MHz。

The deblocking filter algorithm is an important part of the high-efficiency video coding standard(HEVC).The deblocking filter circuit structure implemented by dedicated hardware is difficult to meet the requirements of continuously innovative algorithms.Reconfigurable calculations are both computationally efficient and efficient.Programming flexibility has become a research hotspot.Based on the hybrid drive of instruction stream and data stream,a reconfigurable video array processor(RVAP),a parallel implementation method of a reconfigurable HEVC encoding and deblocking filter circuit was proposed.Based on the analysis of the data flow graph,the maximum parallelism of the deblocking filtering algorithm was realized and the calculation efficiency was improved.The flexible switching of strong/weak filtering methods improved the utilization of computing resources.Experimental results show that the proposed method can reduce hardware resources by 47.6%and the clock frequency reaches 167 MHz while meeting the requirements of flexible algorithm switching and computing speed.