FPGA平台SM3密码杂凑算法的优化设计

Optimization Design of SM3 Cryptographic Hash Algorithm on FPGA Platform

分析了SM3密码杂凑算法基本流程,基于FPGA平台设计开发该算法的高性能硬件实现。以Xilinx公司ARTIX-7系列XC7A100T芯片为核心,采用16个寄存器构成寄存器组作为生成132个字的缓存区,设计进位保留加法器进行关键路径的压缩,使完成一次压缩函数中关键路径计算所需的时钟周期明显减少。实验结果表明,本文方案的吞吐率高达90.54 Gb/s,适用于对吞吐量有较高要求的场景。

The basic flow of SM3 cryptographic hash algorithm is analyzed,a high-performance hardware implementation of SM3 on the field programmable gate array(FPGA)platform is designed.ARTIX-7 series chip of Xilinx is used as the core.We use a cache of 16 registers in a register group.The carry reservation adder is used to compress the critical path,which reduces the clock cycle to complete the critical path calculation in a compression function.The test results show that the throughput rate of the proposed scheme is up to 90.54 Gb/s,which is suitable for scenarios with high throughput requirements.