一种FPGA中高效实现的数字信道化滤波器组结构

An efficient digital channelized filter banks architecture in FPGA

针对数字信道化滤波器组在电子侦察中的应用,提出了一种可在可编程逻辑器件(FPGA)中高效实现的数字信道化滤波器组结构,该结构各处理环节的数据吞吐率与FPGA处理速度一致,有利于充分利用FPGA的运算能力。在电子侦察的典型应用中,FPGA处理速度往往是滤波器组输出数据率的10多倍,相比于传统结构的直接实现,该结构对FPGA处理资源的需求降低一个数量级。

For the EW application,a digital channelized filter banks architecture is proposed,which can be efficiently implemented in FPGA.In this architecture,the data throughput of each part matches with the process⁃ing speed of FPGA,which is conductive to making full use of the computing resources of FPGA.In typical EW applications,the processing speed of FPGA is almost ten times of the output data rate of filter banks.Compared with the direct implementation of traditional architecture,the architecture proposed can reduce the resource re⁃quirements by an order of magnitude.