一种超高PSRR低噪声LDO的设计

Design of an ultra-high PSRR and low noise LDO

针对经典低压差线性稳压器(Low Dropout Regulator,LDO)电源抑制比(Power Supply Rejection Ratio,PSRR)低、输出噪声大的问题,设计了一款采用预稳压调制级加低通滤波结构的LDO。将反馈电阻网络提前加载在电路的低通滤波模块中,使得带隙基准模块噪声和反馈电阻噪声被低通滤波模块滤除,以达到降低噪声的目的。电路采用具有高PSRR带隙基准电路和增大环路低频增益的方式,以提高低频条件下LDO的PSRR。采用零极点追踪电路,在保证LDO稳定性的同时拓展环路带宽,以提高高频段条件下的PSRR。芯片基于5 V 0.18μm互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)工艺设计。仿真结果表明,在频率为1 kHz和100 kHz时,PSRR分别可达-109 dB和-66.7 dB;当负载电流为250 mA时,在10 Hz到100 kHz频率范围内的积分噪声约为6.1μV rms。设计的LDO具有较高的PSRR和较低的噪声。

In response to the problem of low power supply rejection ratio(PSRR)and high output noise in the classic structure of low dropout regulator(LDO),a LDO with pre-regulated modulation stage and low-pass filtering structure is designed.By advancing the feedback resistor network and adding a low-pass filter module to the circuit,the bandgap reference module noise and feedback resistor noise are filtered out by the low-pass filter module to achieve noise reduction.High PSRR bandgap reference circuit and increased loop gain at low frequencies are used to improve the PSRR of the LDO at low frequencies,and zero-pole tracking circuit is used to expand the loop bandwidth and improve the PSRR at high frequencies while ensuring the stability of the LDO.The chip is designed based on a 5 V 0.18μm complementary metal oxide semiconductor(CMOS)process.The simulation results show that the PSRR can reach-109 dB and-66.7 dB at 1 kHz and 100 kHz respectively,and the integration noise in the frequency range of 10 Hz to 100 kHz is about 6.1μV rms when the load current is 250 mA.The designed LDO has high PSRR and low noise.