改进型定制乘法器的优化设计

Optimized design of improved custom multipliers

为了降低乘法器的功耗,提升高性能定制乘法器的整体性能,通过优化booth选择器和CSA42压缩器来实现降低功耗的目的。基于当前先进工艺的条件,对运用上述优化点的无符号16位乘法器进行前仿验证,本文设计的乘法器功耗数据为0.5 mw,最大路径延迟530 ps。由结果可知,本文提出的改进型设计,可以实现降低功耗的目标。

In order to reduce the power consumption of multiplier,improve the overall performance of high performance custom multiplier,the target of reducing power consumption is achieved by optimizing the booth selector and CSA42 compressor.Based on the conditions of the current advanced technology,the pre-verification of the unsigned 16-bit multiplier using the above optimization points is carried out.The power consumption data of the multiplier designed in this paper is 0.5 mw and the maximum path delay is 530 ps.It can be seen from the results that the improved design proposed in this paper can achieve the goal of reducing power consumption.