期刊文献+

基于SATA3.0的高速大容量存储系统设计 被引量:1

Design of High-speed Mass Storge System based on SATA3.0 Interface
下载PDF
导出
摘要 在通信技术快速发展的背景下,数据传输呈现速度快、容量大、带宽高的特点,为解决由此带来的数据缓存问题,设计一款基于SATA3.0协议的高速大容量存储系统。采用Xilinx-Virtex7系列XC7VX690TFFG1158作为控制核心,SRIO协议缓存前级高带宽大容量的数据,同SSD的数据通信采用SATA3.0协议,同上位机之间的数据通信采用RGMII协议。利用FPGA并行处理数据的优点,应用RAID0阵列实现并行控制8块SSD。经实际测试,存储系统平均写入速度大于20 Gb/s,整个SSD阵列平均写入速度可达29.2 Gb/s,平均读取速度可达35.7 Gb/s,在卫星通信等高速数字信号处理领域有广泛应用前景。同时为高速大容量存储系统的设计提供一定的参考意义。 With the rapid development of communication technology,data transmission is characterized by high-speed,large-capacity and high-bandwidth,but data cache can be a problem.In order to solve this problem,a high-speed and largecapacity storage system is designed based on SATA3.0 protocol.Using Xilinx-Virtex7 series chip XC7VX690TFFG1158 as main controller,SRIO protocol is used to cache the data of Pre-device with high bandwidth and large capacity,SATA3.0 protocol is used to communicate with SSD,and RGMII protocol is used to communicate with the host computer.Taking advantage of the parallel processing characteristic of FPGA,RAID_0 array is used to realize the parallel control of 8 SSDS.The test result shows that,for the whole storage system,the average data writing speed is greater than 20 Gb/s,the average write speed of the entire SSD array can reach 29.2 Gb/s,and reading speed can reach 35.7 Gb/s.This storage system has a wide application prospect in the field of high-speed digital signal processing such as satellite communication,and it provides some reference significance for the design of high-speed and large-capacity storage system.
作者 罗艺灵 杜雨洺 李一杰 LUO Yiling;DU Yuming;LI Yijie(College of Electronic Engineering,Chengdu University of Information Technology,Chengdu 610225,China)
出处 《成都信息工程大学学报》 2023年第2期160-165,共6页 Journal of Chengdu University of Information Technology
关键词 FPGA SATA3.0 SRIO RAID_0阵列 GTH收发器 FPGA SATA3.0 SRIO RAID_0 arrays GTH transceiver
  • 相关文献

参考文献10

二级参考文献57

  • 1苏丽,杨先博,余卫国.基于SOPC技术的高速盘阵记录器设计[J].遥测遥控,2012,33(2):63-66. 被引量:1
  • 2张福琼.T/R组件设计与制造[J].现代雷达,1996,18(2):91-97. 被引量:8
  • 3李刚,韩松.大容量高速固态盘设计[J].电子测量技术,2006,29(2):129-130. 被引量:8
  • 4高葆新.微波集成电路[M].北京:国防工业出版社,1995..
  • 5[1]Donald J H.Solid state transmit/receive module for the PAVE PAWS phased array radar[J].Microwave Journal.1978,17(4):33-35.
  • 6[2]Eliot D C.Trends in the development of MMICs and packages for active electronically scanned arrays(AESAs)[C]// 1996 IEEE Int.Symp.On phased array system and technology,[s.l.]:IEEE,1996:1-4.
  • 7[4]张福琼.固态有源相控阵雷达T/R组件专辑[M].南京:机电部14所,1993.
  • 8Ravi Budruk,Don Anderson,Tom Shanley.PCI Express系统体系结构标准教材[M].北京:电子工业出版社,2005
  • 9Fuller S.RapidlO:嵌入式互联系统[M].王勇,林粤伟,吴冰冰,等,译.北京:电子工业出版社,2006.
  • 10孙浩然.高速海量固态硬盘的设计[D].哈尔滨:哈尔滨工程大学,2009.

共引文献43

同被引文献9

引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部