基于列共用多采样技术的CMOS图像传感器读出电路设计

Design of Readout Circuit for CMOS Image Sensor Based on Column Sharing Multiple Sampling

针对CMOS图像传感器中相关多采样(Correlated Multiple Sampling,CMS)技术在抑制噪声的同时使读出速度受影响的问题,设计了低噪声读出电路。读出电路采用列共用多采样技术,能够在不影响读出速度的情况下,抑制时域噪声和列固定模式噪声(Fixed Pattern Noise,FPN),改善CMOS图像传感器的成像质量。列共用多采样技术采用开关控制读出电路和像素的连接关系,以多列共用的读出电路对像素依次进行时序错开时间缩短的多次采样,完成所有像素量化的总时间保持不变。基于列共用多采样技术读出电路的降噪效果在110 nm的CMOS工艺下进行了仿真和验证。随着采样数M从1到4变化,读出时间没有增长,瞬态噪声仿真得到整个读出链路的输入参考噪声从123.8μV降低到60.6μV;加入列FPN进行仿真,输入参考失调电压由138μV降低到69μV。

A low⁃noise readout circuit for CMOS image sensor is designed targeting at the problem that correlated multiple sampling(CMS)affects the readout speed while suppressing noise.The readout circuit is designed based on column sharing multiple sampling technique,which could suppress temporal noise and column fixed pattern noise(FPN)and improve the quality of captured image without affecting readout speed.For column sharing multiple sampling technique,the connection between pixels and readout circuits is controlled by switches,multiple shared readout circuits are used to sample pixels sequentially,the timing of shared readout circuits is staggered and shortened,and the whole time to complete the quantization of all pixels is not getting longer.The readout circuit based on column sharing multiple sampling is designed and simulated in a 110 nm CMOS process,and the noise reduction effect is verified.As the sampling number of M changes from 1 to 4,the length of readout timing remains constant,and the input referred noise decreases from 123.8μV to 60.6μV;while simulating with added column FPN,the input referred offset voltage decreases from 138μV to 69μV.