4H-SiC MOSFET栅氧界面性能提升工艺

Gate-oxide interface performance improvement technology of 4H-SiC MOSFET

MOSFET器件是现代微电子学的关键核心器件之一,其应用范围从高度集成的CMOS芯片到高功率器件.目前,SiC MOSFET存在沟道迁移率较低、阈值电压漂移、栅氧介质在高温下的长期可靠性不足、体二极管正向导通状态下产生双极型漂移等问题.值得注意的是,其中众多问题都与栅氧界面缺陷有关.由于SiC/SiO_(2)界面缺陷的存在,SiC MOSFET器件的沟道迁移率被严重限制,栅氧化层的可靠性和阈值电压的稳定性也受到较大影响,导致其栅氧界面性能较差.为了改善这些问题,本文从退火、高k介质层的使用、栅氧化物掺杂、沟槽型MOSFET沟槽深宽优化四个方面,综述了提升4H-SiC MOSFET栅氧界面性能的制备工艺,从多个角度介绍了多种可行的方案,以期进一步综合提升4H-SiC MOSFET栅氧界面性能,使其更好地应用于电力电子系统.

MOSFET devices are one kind of the core devices of modern microelectronics,with applications ranging from highly integrated CMOS chips to high power devices.As a third-generation wide bandgap semiconductor material,SiC has excellent electrical properties such as wide bandgap,high breakdown electric field,and high temperature resistance.The application of 4H-SiC MOSFET devices in power electronics systems can significantly enhance the reliability and reduce the power consumption of the system,which makes 4H-SiC MOSFETs have a wide application prospect in power electronics systems.Nowadays,SiC MOSFETs suffer from low channel mobility,threshold voltage drift,insufficient longterm reliability of the gate oxygen dielectric at high temperatures,and bipolar drift in the forward-guided state of the body diode.Remarkably,many of these problems are related to defects at the gate-oxide interface.Owing to the presence of SiC/SiO_(2)interface defects,the channel mobility of SiC MOSFET devices is grossly limited,and the reliability of the gate-oxide layer as well as the stability of the threshold voltage are also significantly affected,contributing to the poor performance of the gate-oxide interface.For instance,partial traps will become charged centers upon electron capture,which leads to enhanced Coulomb scattering effects on the surface of the channel and consequently reduced channel mobility.Decreasing the thickness of the gate-oxide layer can enhance the current driving capability of the transistor and boost the switching speed as well as the power characteristics.However,a thin oxide layer will aggravate the tunneling effect of the electron and make the oxide layer unreliable.To ameliorate these concerns,this review presents a number of processes for gateoxide interface performance enhancement of 4H-SiC MOSFETs from four aspects:Annealing,utilization of high-k dielectric layers,gate oxide doping,and trench-type MOSFETs’trench depth-width optimization,along with an analysis of the effects of these processes on 4H-SiC MOSFETs.The annealing process can reduce the defects at the gate-oxide interface to a certain extent,enabling the interface density of states to be diminished and thus enhancing the channel carrier mobility.For a specific gate dielectric thickness,the application of high-k gate dielectric material dramatically reduces the electric field value,thereby reducing the total gate current density and increasing the reliability of the gate-oxide layer.Doping of different ions in the gate oxide is effective in passivating SiO_(2)/SiC interfacial traps and upgrading carrier mobility.As for trench MOSFETs,according to the influence of breakdown voltage and on-resistance with the change of groove depth and width,better FOM value can be found by continuing to optimize the width and depth of the gate,so as to further promote the reliability of trench MOSFETs.This paper reviews various feasible alternatives from several perspectives in order to further comprehensively improve the performance of 4H-SiC MOSFET gate-oxide interface for better applications in power electronics systems.