12 bit 100 MS/s Flash-SAR混合模数转换器设计

Design of a 12 bit 100 MS/s Flash-SAR Hybrid Analog-to-Digital Converter

针对传统逐次逼近型模数转换器(Successive Approximation Register Analog-to-Digital Converter,SAR ADC)采样率和能量效率低等问题,设计了一款快闪型(Flash)与逐次逼近型(SAR)相结合的新型混合架构模数转换器。利用快闪型ADC一个时钟周期内可以转换出多个数字码的优势,提高了ADC的采样率。采用新型混合开关切换策略与分段电容阵列技术相结合提升了ADC的能量效率,减小了版图面积。同时,电路采用预放大动态锁存比较器以降低噪声和失调对ADC性能的影响。采用SMIC 0.11μm工艺后,仿真结果表明,在1.2 V的工作电压下,当采样速率为100 MS/s,输入信号频率为45.04 MHz时,输出信号的信号噪声失真比(Signal-to-Noise-and-Distortion Radio,SNDR)为69.26 dB,无杂散动态范围(Spurious-free Dynamic Range,SFDR)为82.10 dB,有效位数(Effective Numbers of Bits,ENOB)达到11.21 bit,功耗为5.72 mW,版图尺寸为380μm×110μm。

To address the low sampling rate and energy efficiency of traditional successive approximation Analog-to-Digital Converters(ADC),a novel analog-to-digital converter with flash and successive approximation hybrid architecture is designed.The sampling rate of the ADC is improved by taking advantage of the fact that Flash ADC can convert multiple digital codes in one clock cycle.The combination of a novel hybrid switching strategy and the split capacitor array technology improves the energy efficiency of the ADC and reduces the chip area.Meanwhile,a dynamic latch comparator with a pre-amplified structure is designed to reduce the effects of noise and offset on ADC performance.The simulation results show that,by using SMIC 0.11μm CMOS technology,at the operating voltage of 1.2 V and when the sampling rate is 100 MS/s and the input signal frequency is 45.04 MHz,the SNDR is 69.26 dB,the SFDR is 82.10 dB,the ENOB is 11.21 bit,the power consumption is 5.72 mW and the layout area is 380μm×110μm.