基于FPGA的差分延迟时间测量电路设计

Design of Differential Delay Time Measurement Circuit Based on FPGA

等精度同步法是频率测量的常用方法,但是计数闸门和基准时钟信号的不同步会产生一个时间间隔,导致最终出现一个字的量化误差。为了减小该误差,提出一种基于FPGA的全数字差分延迟TDC(time-to-digital converter)电路。文中TDC基于差分延迟线原理,构建2条时延不同的延迟线代替传统单线延迟,提高了测量分辨率。设计数字校准电路,减少测量过程中外界条件变化造成的误差,试验结果表明:25℃下TDC单次测量绝对误差小于90 ps。

The equal-precision synchronization method is a common method for frequency measurement,but the unsynchronization of the counting gate and the reference clock signal will produce a time interval,resulting in the final quantization error of one word.In order to reduce the error,a time-to-digital converter(TDC)circuit based on FPGA was proposed.Based on the principle of differential delay line,the TDC constructed two delay lines with different delay to replace the traditional single line delay,and improved the measurement resolution.The digital calibration circuit was designed to reduce the error caused by the change of external conditions in the measurement process.The test results show that the absolute error of TDC measurement is less than 90 picoseconds at 25℃.