摘要
Short circuit fault occurrence in high-voltage DC (HVDC) systems causes extremely high currents in a fast raising time that does not experience current zero-crossing. To protect HVDC systems/grids against fault current, fast HVDC breaker is an essential equipment. This study presents the design procedure of a novel HVDC breaker based on solid-state controllable reactor which is able to reduce the fault current's rate of rise and fault current amplitude to less than grid nominal current in the breaking process. The main achievement of the proposed HVDC breaker is that not only breaker does not encounter fault current, but also none of the series HVDC equipment is influenced by the fault. The designed breaker performance is studied by PSCAD/EMTPS, and then the simulation results are validated by the developed laboratory experimental setup.
