DTRC:针对变频时钟功耗优化片上谐振网络

DTRC:resonant network for clocking power optimization under frequency scaling system

针对片上谐振时钟网络在变频环境下功耗优化能力减弱问题,提出了一种基于可调数字延时控制单元的谐振时钟网络结构———关断调节式谐振时钟电路(DTRC),该结构可有效改善谐振电路在变频环境下的整体功耗优化情况。产生这一问题的根本原因是在系统电感和电容值确定后,电路本征谐振频率固定,对于传统结构,当时钟工作频率偏移谐振频率,谐振电路功耗优化能力减弱,甚至恶化。本文在12 nm Fin-FET工艺下实现完整时钟分布网络(CDN),后仿结果表明,通过调整谐振电路驱动单元关断时间,在时钟1~5 GHz频率范围内,相比传统无谐振电路实现18%~46%功耗优化,相比已有谐振时钟电路实现13%~54%功耗优化。

Aiming at the deterioration of power consumption optimization of on-chip resonant clock network working under variable-frequency,a resonant clock network structure based on an adjustable digital delay control unit——dead-timing tuning resonant clock(DTRC)is proposed.This structure can effectively improve the overall power con-sumption optimization of resonant circuit at different frequencies.The key point of the problem is that the intrinsic resonant frequency of the circuit is fixed once the system inductance and capacitance are determined.For the tradi-tional structures,the power consumption optimization capability of the resonant circuit is weakened or even deterio-rated after the clock working frequency deviating from the resonant frequency.This paper achieves a complete clock distribution network(CDN)under 12 nm Fin-FET process.Post-simulation indicates that the power consumption can be reduced by 18%~46%compared with conventional no-resonant circuits and 13%~54%compared with conventional resonant clock circuit,within the clock frequency of 1~5 GHz,by adjusting the delay time of the driving units in the resonant circuit.