SoC随机化系统验证场景自动产生方法及实现

Automatic Generation of Randomized System Scenarios for SoC Verification

SoC(System on Chip)特别是大规模数据通信芯片包含较多接口模块,可配置成的端口(Port)数量大、速率种类多;在实际应用中当芯片和对端设备连接时,有非常丰富的端口配置组合模式,需要海量的验证场景以确保芯片在流片前的设计质量。当前的随机化仿真验证如UVM(Universal Verification Methodology)一般只对数据会话(Transaction)配置进行随机,很难覆盖如此丰富的接口模式和系统场景组合,这给芯片验证方法和EDA(Electronic Design Automation)工具带来了巨大的挑战。本文介绍了一种随机化系统场景激励自动产生方法,灵活构造系统级验证平台,可对待测芯片设计DUT(Design Under Test)仿真时动态调整,并通过场景随机化实现完全覆盖验证。本方法已完成开发、并应用于百亿级晶体管SoC芯片仿真验证,在流片前及时发现了多个芯片设计RTL(Register Transfer Level)问题,有效提升了具有复杂接口和多种配置组合系统场景的SoC开发质量。

SoC,especially for large scale data communication IC,usually comprises of a large number of network interface modules,which can be configured into different port combinations with kinds of speed rates when the chips are connected with pear devices in practical applications.Currently the pre-silicon simulation like UVM just supports randomization of data transactions,and it is not easy to cover such rich scenario combinations of interface modes,which brings huge challenges to pre-Silicon verification and results in high risk on RTL code quality.This paper introduces a self-developed new method which can automatically generates randomized scenario stimulus to build system level verification platform flexibly.These scenario configurations can be dynamically adapted during simulation,and can approach complete coverage for both data transactions and system scenarios.This method has been implemented and proven on SoC verification with tens of billions of transistors inside,which effectively and efficiently improved SoC development quality.