Magpie 加密算法FPGA 实现及优化研究

FPGA Implementation and Optimization of Magpie Encryption Algorithm

攻击者对物联网中的设备进行监听、俘获、窃取以及修改等,导致用户关键数据的安全性和隐私性受到严重威胁。如何在资源受限的物联网设备上保证数据安全,同时又有较低的实现面积,成为加密算法设计实现的一个挑战。本文以高安全轻量级分组密码算法Magpie为研究对象,在分析其加密流程和原始设计的基础上,提出一种基于FPGA的实现方案。新的设计方案中,复用密码算法轮运算中的各个电路模块,并将密钥更新与轮运算并行设计。在Xilinx Virtex-5 xc5vlx50t上实现了该算法,其频率达到了226 MHz,面积缩减到2704slices。与原始设计方案相比,大大减少了电路面积,并提高了密码算法的运行速度,为物联网设备的安全设计提供参考。

The attackers monitor,capture,steal and modify devices in the Internet of Things,which seriously threatens the security and privacy of users’key data.How to keep data secure on resource-constrained devices and at the same time,the hardware resource consumption is less.It becomes a challenge for the design and implementation of encryption algorithm.Based on the analysis of the Magpie encryption process and the original design,this paper proposes an implementation scheme of FPGA.In the new design,each circuit module in the round operation of the cryptographic algorithm is reused,and the key update is designed in parallel with the round operation.The algorithm is implemented on Xilinx Virtex-5 xc5vlx50t,and its frequency reaches 226MHz and its area is reduced to 2704slices.Compared with the original design,the circuit area is greatly reduced and the speed of the cryptographic algorithm is improved,which provides a reference for the security design of Internet of Things devices.