在FPGA上实现FFT的高效串行流水线结构

Implementation of FFT on FPGA with an Efficient Serial Pipeline Structure

提出在FPGA上实现频域切分基4-FFT的一种设计方案,采用串行流水线结构,适用于连续信号的分段FFT。通过巧妙设计每级蝶形变换的数据序列,无需码位倒置排序即可得到自然序FFT结果,与码位倒置排序实现方法相比,节省硬件资源同时降低运算时间。该结构可直接用于4的次幂点FFT,且稍加改动即可用于2的次幂非4的次幂点FFT。

A design for implementing frequency domain segmentation base 4-FFT on FPGA was proposed in this paper.The design scheme adopts serial pipeline structure and is suitable for segmented FFT of continuous signals.After delicately designing the data sequence of each butterfly transformation,the natural sequence FFT results are obtained without bit reversion,which saves hardware resources and reduces the operation time compared to conventional implementation methods.This structure can be directly used for power 4 FFTs,and can also be used for power 2 FFTs if slight modifications are made.