面向功能向量的并行逻辑模拟

Parallel Logic Simulation for Functional Test

为了提高数字系统中功能向量的模拟效率并获得良好的性能扩展性,提出一种并行逻辑模拟算法.首先针对异质计算中图形显卡和多核微处理器的架构特性,结合同层级逻辑门仿真的任务并行性和竞争包容的事件管理机制;然后采用基于位操作的门运算、基于时帧的模拟以及基于VCD的功能向量进行逻辑仿真.在超百万门的开源电路openMSP和ISCAS89上的实验结果表明,对比单线程算法,功能向量模拟可以获得8.9~86.8的性能加速比,且加速比与电路的规模成正比.

To improve the efficiency of functional test simulation in digital systems with good performance scalability,an algorithm of parallel logic simulation is proposed.By tailoring to the architectural feature of graphics cards and multi-core microprocessors in heterogeneous computing,the algorithm combines task parallelism in gate evaluation at the same level and a race-tolerant mechanism for event management.It makes use of bitwise logical operation-based gate evaluation,frame-based simulation,and VCD-based func-tional test stimulus.Experiments are conducted on open-source circuits of openMSP and ISCAS89 with over one million gates.Compared to the single-threaded algorithm,a performance speedup of 8.9 to 86.8 can be achieved;moreover,the speedup is proportional to the size of the circuit.