轻量级序列密码算法lizard的FPGA设计与优化

Design and Optimization of Lizard Lightweight Stream Cipher Based on FPGA

Lizard序列密码算法作为类似eSTREAM组合中Grain的算法,由于较小的内部状态,具有较好的硬件实现优势。为了在硬件层面提高该算法实现的工作频率,同时一定程度上降低资源消耗,本文使用Verilog硬件语言对该算法进行FPGA实现,并提出两种设计方案。首先,本文基于二段式有限状态机设计了算法实现的基础版本。其次,本文在基础版本设计的基础上通过对密码Lizard算法的原理分析,完成了算法6比特并行版本的设计,进一步提高了算法运行的吞吐率。最后,在Vivado 2019.2.1环境中采用赛灵思公司的Spartan7系列的硬件平台XC7S50FGGA484-1芯片,使用Verilog硬件设计语言对密码Lizard算法两种设计版本进行设计、综合和实现,再通过ModelSim 10.4进行仿真验证,结果表明两种设计的工程实现结果与标准测试向量相同。性能测试结果显示:在基础版本中,Lizard序列密码算法实现了最小的面积消耗,最高工作频率达到221MHz;在并行版本中,Lizard序列密码算法实现最大的吞吐量可达1254Mbps,提高了数据加密运算的速率。

As an algorithm similar to the Grain in the eSTREAM combination,Lizard stream cipher al-gorithm has the advantage of preferable hardware implementation due to minor internal state.To increase the working frequency of algorithm implementation on the hardware level and reduce the resource con-sumption to some extent,algorithm implementation of the Lizard stream cipher algorithm on FPGA using the Verilog hardware language is discussed in this paper,and two implementation versions are proposed.A basic version based on the two-stage finite state machine is first designed,based on which a 6-bits parallel version is then designed by analyzing the principle of the Lizard stream cipher algorithm to further improve the algorithm throughput.Finally,design,syntheses and implementation of the two versions are realized in Vivado 2019.2.1 software environment with the Xilinx's Spartan7 serial XC7S50FGGA484-1 chip as the hardware platform.Simulation validation is performed using the Model-Sim 10.4.Test shows that project realizations of the two design versions accomplish same results as the standard test vectors.The basic version achieves the smallest area consumption and the maximum working frequency reaches 221MHz.The parallel version achieves a maximum throughput of 1254Mbps,which improves the data encryption speed.