基于电源分配网络仿真确定封装电容的方法

Determination of Packaging Capacitance Based on Power Distribution Network Simulation

在FPGA、CPU、GPU、DSP等产品的封装设计中,不仅需要考虑信号的完整性,还需要考虑电源分配网络。集成电路封装会增加芯片电源网络的电感,导致芯片性能下降,影响器件的质量。由于封装空间的限制与基板阻抗的要求,在封装基板上贴装符合设计的去耦电容以降低阻抗,对满足芯片性能要求至关重要。采用SIwave与ADS等软件工具对配电网络进行仿真,通过时域和频域两种分析方法可快速确定整个供电网络是否满足芯片的供电需求。

In the packaging design of products such as FPGA,CPU,GPU and DSP,not only the integrity of the signal needs to be considered,but also the power distribution network needs to be considered.Integrated circuit packaging can increase the inductance of the chip power network,leading to a decrease in chip performance and affecting the quality of the devices.Due to the limitation of packaging space and the requirements of substrate impedance,mounting designed decoupling capacitors on the packaging substrate to reduce the impedance is critical to meet the chip performance requirements.SIwave and ADS and other software tools are used to simulate the distribution network,both time-domain and frequency-domain analysis methods can quickly locate whether the entire power supply network meets the power supply needs of the chip.