基于Surrogate模型的断言覆盖技术研究

A Surrogate model-based assertion coverage improvement technology

随着集成电路设计规模不断增大,验证成为制约设计进程的瓶颈之一。目前,仿真仍是集成电路设计验证的主导方法之一,仿真的完备性通常通过各种覆盖率测度来度量。功能覆盖率是抽象层次较高的一种覆盖率,实际工程中,功能常以SystemVerilog断言形式呈现。目前常用的随机测试向量生成较难生成大量激活断言的测试向量;而采用约束求解的策略时,一旦覆盖条件中涉及到非初始输入信号(内部信号、输出信号),约束求解的效率将极为低下,导致仍然难以覆盖目标断言。针对含非初始输入信号断言的覆盖问题,提出了一种利用Surrogate模型的断言覆盖率提升方法,主要是为非初始输入信号生成体现其与初始输入信号关系的、只包含初始输入信号的Surrogate模型,再以此Surrogate模型作为约束求解的对象,降低了约束求解的复杂度。实验结果表明,相比于随机测试向量生成,该方法在断言覆盖方面有较大提升。

As the scale of integrated circuit design continues to increase,verification has become one of the bottlenecks in the design process.Currently,simulation is still one of the dominant methods for integrated circuit design verification,and the completeness of simulation is usually measured by various coverage metrics.Functional coverage is a higher level of coverage,and in practical engineering,functions are often presented in the form of SystemVerilog assertions.Currently,it is difficult to generate a large number of test vectors that activate assertions using commonly used random test vector generation methods.When using constraint solving strategies,if the coverage condition involves non-initial input signals(internal signals,output signals),the efficiency of constraint solving will be extremely low,making it still difficult to cover the target assertion.To address the coverage problem of assertions containing non-initial input signals,this paper proposes a Surrogate model-based assertion coverage improvement method,which mainly generates a Surrogate model that reflects the relationship between non-initial input signals and initial input signals and only contains initial input signals,and then uses this Surrogate model as the object of constraint solving,thus reducing the complexity of constraint solving.Experimental results show that this method has a significant improvement in assertion coverage compared to random test vector generation.