一种基于混合加固的容软错误NoC路由器

A hybrid-hardening soft error tolerant NoC router

片上网络已成为众核处理器互连网络的标准范式。然而,随着电源电压的逐渐降低,工艺尺寸的逐渐缩减,片上网络中出现软错误的概率逐渐增大。错误纠正码常用于容软错误的片上网络路由器设计中。然而,传统的路由器设计往往只采用汉明码进行纠错,这样的设计结构简单却存在纠错能力不足的问题。提出了一种基于错误纠正码的混合加固容软错误路由器设计方案,该设计方案的核心思想是,依据信息位重要性的不同,采取不同的容错码设计,实现了路由器可靠性与容错开销之间的权衡。实验结果显示,该设计方案相较于基准设计在合成流量和PARSEC benchmark下实现了系统可靠性的提升;同时,硬件综合结果也表明该设计方案可以缩短4%的关键路径延迟。

Networks-on-Chip(NoC)has become the standard paradigm for interconnect networks in multi-core processors.However,as the power supply voltage gradually decreases and the process size is reduced,the probability of soft errors in NoC increases.Error correction codes are commonly used in NoC router designs to tolerate soft errors.However,traditional router designs often only use Hamming codes for error correction,which has the problem of insufficient error correction capability,despite its simple design structure.This paper proposes a hybrid-hardening NoC router design based on error correction codes.The core idea of this design is to adopt different fault-tolerant code designs based on the importance of information bits,thus achieving a balance between router reliability and fault-tolerant overhead.Experimental results show that our design improves system reliability compared to the baseline design under synthetic traffic and PARSEC benchmark,and the hardware synthesis results also show that this design can shorten the critical path delay by 4%.