基于CE/TOL的星载跳频处理器公差分析与优化

Tolerance Analysis and Optimization of Satellite-borne Frequency Hopping Processor Based on CE/TOL

使用公差分析软件CE/TOL,将星载跳频处理器子板连接器间距作为封闭环建立公差分析模型。通过敏感度和贡献度分析,确定经验设计时影响封闭环公差的关键尺寸,通过改进结构构型将其从装配尺寸链中剔除;通过测量变异分析,对改进后构型的组成环公差进行优化,依据随机误差极限值原理将连接器对插合格率提高到99.73%。CE/TOL可以量化分析零部件的安装方式以及尺寸公差的改变对整机连接器对插精度的影响,这为复杂拼装式电子产品对插可靠性设计提供了可借鉴的设计思路。

Using the tolerance analysis software CE/TOL,the tolerance analysis model is established by taking the distance between the sub-boards of the frequency hopping processor as the closed loop.Through the analysis of sensitivity and contribution,the key dimensions that affect the tolerance of the closed loop in empirical design are determined and removed from the assembly dimension chain by improving the structural configuration;through measurement variation analysis,the tolerance of the composition loop after improvement is optimized,the connector insertion success rate is increased to 99.73%according to the principle of limit value of random error.CE/TOL can quantitatively analyze the influence of the installation mode of parts and the change of dimension tolerance on the connector insertion success rate of the product,which provides a reference design idea for the plug-in reliability design of complex assembled electronic products.