基于开关电容放大器的低面积开销ADC

Area-Efficient ADC Based on Switched-Capacitor Amplifier

针对模数转换器(ADC)在存内计算芯片中面积占比大的问题,提出了一种基于开关电容放大器的低面积开销ADC,包括一个全局数模转换器(GDAC)和基于开关电容放大器的局部列级ADC。整体电路采用单端逐次逼近型(SAR)ADC架构,利用开关电容放大器实现电压的逐次逼近,大幅度减少了单位电容数量,降低了局部列级ADC的整体面积开销;局部列级ADC共用由GDAC同步产生的参考电压,提高了ADC的整体面积效率。基于55nmCMOS工艺设计了单列8位ADC,电源供电电压为1.2V,输入电压范围为200~800mV,在2.22MSa/s的采样速率下,其功耗为205μW,面积为3537μm^(2)。仿真结果表明,单列ADC的有效位数为7.86bit,无杂散动态范围为64.3dB,品质因数(FoM)为1405pJ·μm^(2)/conv。

Aiming at the problem of the large area share of analog-to-digital converter(ADC)in the computing-in-memory chip,an area-efficient ADC based on the switched-capacitor amplifier is proposed,which includes a global digital-to-analog converter(GDAC)and local column parallel ADCs based on the switched-capacitor amplifier.The whole circuit adopts the single-ended successive approximation register(SAR)ADC architecture and realizes successive approximation of voltage by the switched-capacitor amplifier,which significantly reduces the number of unit capacitors and the overall area cost of the local column parallel ADCs.The local column parallel ADCs share the reference voltage synchronously generated by the GDAC,which further improves the overall area efficiency of the ADC.A single-column 8-bit ADC is designed based on the 55 nm CMOS process.The power supply voltage is 1.2 V,the input voltage range of the ADC is 200-800 mV,the power consumption is 205μW at the sampling rate of 2.22 MSa/s,and the area is 3537μm^(2).The simulation results show that the effective number of bits is 7.86 bit,the spurious free dynamic range is 64.3 dB,and the figure of merit(FoM)is 1405 pJ·μm^(2)/conv.