2.2 GHz锁相环集成电路

2.2 GHz phase-locked loop integrated circuit

为满足高速数据传输系统对高速低抖动采样时钟的需求,通过Simulink行为级建模验证和Cadence工具设计仿真,基于TSMC 180 nm BCD工艺设计制造了2.2 GHz电荷泵锁相环芯片,并进行了测试。锁相环电路在电荷泵中采用带反馈运算放大器的低漏电流结构,获得精准稳定的充放电电流;在压控振荡器中采用具有对称负载特性的延时单元及带反馈的自偏置电路,提高抗噪声能力。锁相环在1.8 V工作电压下,输入基准时钟为50 MHz时,功耗为32 mW,输出时钟频率为2.2 GHz,均方根抖动为1 ps;在1 MHz频率偏移量下,相位噪声为-87.84 dBc/Hz;在10 MHz频率偏移量下,相位噪声为-112.55 dBc/Hz。测试结果表明,所设计的锁相环电路可稳定输出低噪声的2.2 GHz时钟信号。

To meet the demand of high-speed and low-jitter sampling clock for high-speed data transmission system,a 2.2 GHz charge-pump phase-locked loop chip was designed and fabricated based on the TSMC 180 nm BCD process,where Simulink behavior-level modeling verification and Cadence tool design simulation were used.The chip was then tested.In the phase-locked loop,a low leakage current structure with feedback operational amplifier was adopted in the charge pump to obtain accurate and stable charge and discharge current.A delay unit with symmetrical load characteristics and a self-biasing circuit with feedback were used in voltage-controlled oscillators to improve noise immunity.When the phase-locked loop is operated at 1.8 V and the input reference clock is 50 MHz,the power consumption,output clock frequency,root mean square jitter,phase noise are 32 mW,2.2 GHz,1 ps,-87.84(-112.55)dBc/Hz at a 1(10)MHz frequency offset,respectively.The test results show that the designed phase-locked loop circuit can stably output a low-noise 2.2 GHz clock signal.