摘要
随着互联网的数据量呈爆炸式增长,以纯软件方式运行的SM4算法速度慢、CPU占用率高,而基于Verilog/VHDL实现的现场可编程门阵列或专用集成电路存在灵活性差、升级维护困难等问题。为了解决上述问题,提出了一种SM4国密算法的异构可重构计算系统的设计方案,采用高层次综合和异构可重构技术,通过优化数据内存分配与传输、优化循环、矢量化内核以及增加计算单元等方式,设计了SM4算法电子密码本模式和计数器模式的定制计算架构,并将该系统部署在FPGA异构平台。实验结果表明:SM4-ECB和SM4-CTR两种主流工作模式的定制计算架构在Intel Stratix 10 GX2800上,吞吐率分别达到109.48 Gbps和63.73 Gbps,是Intel Xeon E5-2650 V2 CPU上对应模式吞吐率的232.63倍和141.62倍。以此核心模块(包含数据输入、加解密、输出)的整体异构可重构计算系统的性能也分别达到了纯软件方式的4.90倍和3.56倍。该方案不仅实现了针对特定模式进行定制加速,而且可以通过硬件重构灵活支持不同的计算模式,兼顾了系统的灵活性和高效性。
With the explosive growth of the data volume of the Internet,there are problems such as the slow speed and high CPU utilization of the SM4 algorithm running in pure software mode.While the field programmable gate array or dedicated integrated circuit based on Verilog/VHDL has problems such as poor flexibility and difficulty in upgrading and maintenance.In order to solve the above problems,this paper proposed a design scheme of heterogeneous reconfigurable computing system based on SM4 algorithm.Using high-level synthesis and heterogeneous reconfigurable technology,it designed the customized computing architecture of SM4 algorithm’s electronic cipher book mode and counter mode by optimizing the allocation and transmission of data memory,optimizing the loop,vectorizing the kernel and adding computing units.And the system was deployed on the FPGA heterogeneous platform.The experimental results show that the customized computing architecture of SM4-ECB and SM4-CTR,two mainstream operating modes,on the Intel Stratix 10 GX2800,has a throughput of 109.48 Gbps and 63.73 Gbps respectively,which is 232.63 times and 141.62 times throughput of the corresponding mode on the Intel Xeon E5-2650 V2 CPU.The performance of the whole heterogeneous reconfigurable computing system composed of this core module,including data input,encryption and decryption,and output,has also reached 4.90 times and 3.56 times of that of pure software mode.This paper not only realizes customized acceleration for specific modes,but also flexibly supports different computing modes through hardware reconfiguration,taking into account the flexibility and efficiency of the system.
作者
王腾腾
柴志雷
Wang Tengteng;Chai Zhilei(School of Artificial Intelligence&Computer Science,Jiangnan University,Wuxi Jiangsu 214122,China;Jiangsu Provincial Enginee-ring Laboratory of Pattern Recognition&Computational Intelligence,Wuxi Jiangsu 214122,China)
出处
《计算机应用研究》
CSCD
北大核心
2023年第9期2826-2831,共6页
Application Research of Computers
基金
国家自然科学基金资助项目(61972180)