面向CMOS图像传感器芯片的3D芯粒(Chiplet)非接触互联技术

3D Contactless Chiplet Interconnects for CMOS Image Sensor

在后摩尔时代,3D芯粒(Chiplet)通常利用硅通孔(TSV)进行异构集成,其复杂的工艺流程会提高芯片制造的难度和成本。针对背照式(BSI)CMOS图像传感器(CIS)的倒置封装结构,该文提出了一种低成本、低工艺复杂度的3D Chiplet非接触互联技术,利用电感耦合构建了数据源、载波源和接收机3层分布式收发机结构。基于华润上华(CSMC)0.25μm CMOS工艺和东部高科(DB HiTek)0.11μm CIS工艺,通过仿真和流片测试验证了所提出的互联技术的有效性。测试结果表明,该3D Chiplet非接触互联链路采用20 GHz载波频率,收发机通信距离为5~20μm,在数据速率达到200 Mbit/s时,误码率小于10^(-8),接收端功耗为1.09 mW,能效为5.45 pJ/bit。

In the post-Moore era,3D Chiplet clusters are typically integrated heterogeneously using Through Silicon Vias(TSVs),whose complex flow increases the difficulty and cost of chip manufacturing.Based on the upside-down packaging of BackSide-Illuminated(BSI)CMOS Image Sensors(CIS),a 3D Chiplet non-contact interconnection technique with low-cost and low packaging complexity is proposed.Using inductive coupling,a three-layer distributed transceiver structure of data source,carrier source,and receiver is constructed.Based on CSMC 0.25 mm CMOS process and DB-HiTek 0.11 mm CIS process,the feasibility of the proposed interconnects is verified by simulation and chip measurement.The test results show that the 3D Chiplet non-contact link can cover 5~20 mm communication distance with 20 GHz carrier frequency,achieving a BER of less than 10^(-8) at the data rate of 200 Mbit/s.The power consumption of the receiver is 1.09 mW,and the energy efficiency of it is 5.45 pJ/bit.