异构多核DSP芯片的可测性设计

DFT solution for a Heterogeneous Multi-core DSP Chip

本文介绍了一款异构多核DSP芯片的可测性设计实现,包含存储器内建自测试、存储器修复、扫描链设计、测试压缩和全速扫描测试。文章首先对芯片架构和可测性设计难点进行了介绍,并制定了全芯片可测性设计的策略,随后介绍了具体的实现,最后给出了覆盖率结果。实验结果表明该设计的测试覆盖率符合工程应用要求。

This paper introduces the DFT solution for a heterogeneous multi-core DSP chip,including memory built-in-self-test,memory repair,scan chain design,test compression and full speed scan test.This paper first introduces the chip architecture and testability difficulties,and formulates the DFT strategy of whole chip,then introduces the concrete implementation process,and finally gives the coverage results.Experimental results show that the coverage of design meets the requirements of engineering application.