基于数字自校准的14位SAR ADC的设计

Design of 14-bit SAR ADC based on digital self-calibration

为了降低电容型模数转换器(ADC)中的电容失配带来的非线性影响,提出了一种基于复用低位电容自校准的逐次逼近型(SAR)ADC电路结构,利用低位电容转化高位电容失配引起的误差电压,实现高位电容失配校准。在55 nm CMOS工艺下实现了该ADC结构。该结构ADC工作过程为失调误差提取与正常转换两阶段,失调误差提取阶段中利用低位电容将高位电容失配产生的误差电压转换为误差码并存储,将误差码与正常转化数字码求和得到最终的数字输出,实现电容失配自校准。为了提高ADC采样速率,该结构通过分段结构将电容阵列分为三段降低了单位电容数量。仿真结果表明,在1.2 V电源电压,80 MSPS采样速率下,引入电容失配后电路功耗为3.72 mW,有效位数为13.45 bit,信噪失真比(SNDR)为82.75 dB,相比未校准分别提高4.41 bit,26.58 dB。

In order to reduce the nonlinear effects of capacitor mismatch in capacitive analog-to-digital converters(ADC),a SAR ADC circuit structure based on the self-calibration of multiplexed low capacitance is proposed.The low capacitance converts the error voltage caused by the mismatch of high capacitance to realize the calibration of high capacitance mismatch.The ADC structure is implemented by 55 nm CMOS technology.The working process of ADC with this structure consists of two stages:extraction of mismatch error and normal conversion.In the extraction stage of mismatch error,the error voltage generated by mismatch of high capacitance is converted into error code and stored by switching of low capacitance.The sum of error code and normal conversion digital code is obtained to obtain the final digital output and realize self-calibration of capacitance mismatch.In order to improve the ADC sampling rate,the structure reduces the number of unit capacitance by dividing the capacitor array into three segments.The simulation results show that the circuit power consumption is 3.72 mW,the ENOB is 13.45 bit,and the SNDR is 82.75 dB at the supply voltage of 1.2 V and sampling rate of 80 MSPS after capacitor mismatch is introduced,which are 4.41 bit and 26.58 dB higher than those without calibration respectively.