分簇式VLIW密码专用处理器的编译器后端优化研究

Optimizing Compiler Back-end for Clustered VLIW Cryptographic Processor

密码专用处理器常采用分簇式超长指令字(Very Long Instruction Word,VLIW)架构,其性能的发挥依赖于编译器的实现.当前对于通用VLIW架构的编译后端优化方案,在密码专用处理器上都有一定的不适应性.为此,本文提出了一种面向密码专用处理器的、同时进行簇指派、指令调度和寄存器分配的编译器后端优化方法.构造“定值-引用”链,求解变量的候选寄存器类型集合交集,确定其寄存器类型;实时评估可用资源,进行基于优先级的指令选择和基于平衡寄存器压力的簇指派;改进线性扫描算法,基于变量的“待引用次数”列表进行实时的寄存器分配.实验结果表明,本方法能够提升生成代码的性能,且算法是非启发式的,减小了编译所需的时间.

Clustered Very Long Instruction Word(VLIW)architecture is widely adopted in cryptographic processors and compilers dominate the performance of those.In this paper,an optimizing framework of compiler back-end for cryptographic processors is proposed,that integrates the cluster assignment,instruction scheduling,and register allocation steps into a single phase.This approach determines the variable′s register type by constructing a use-def chain and finding the intersection of candidate register types sets.Within the available resources,priority-based instruction selection is performed and cluster assignment aiming at balanced register pressure is conducted.The linear scan algorithm is revised to implement a real-time register allocation based on the list of remaining use.The whole process is non-heuristic,so it avoids successive iterations.Experimental results show that the proposed technique is capable of generating more efficient code than previously proposed techniques for it allows global optimization.