单层MoS_(2)全包覆晶体管的电学性能极限

Performance limit of all-wrapped monolayer MoS_(2)transistors

基于二维过渡金属硫化物的全包覆晶体管是后硅时代的理想电子器件,从玻尔兹曼输运理论出发,在考虑载流子的主要外秉散射机制后,针对三种典型的栅介质(Al_(2)O_(3),HfO_(2)和BN)构筑的单层MoS_(2)晶体管的电学性能进行了系统的理论研究。为解决介质中表面光学声子散射被高估这一常见问题,使计算更为准确,在电介质和沟道间的建模中引入了“死区”概念。重点针对微电子1nm及以下技术节点用途晶体管的电荷迁移率和电流密度等指标进行了探讨.研究表明,在沟道长度小于10nm的情况下,晶体管开态电流均可超2mAμm。上述结果阐明了基于单层半导体构筑晶体管在终极微缩条件下的性能潜力,对深度摩尔器件设计具有一定的参考价值。

All-wrapped transistors consisting of two-dimensional transition-metal dichalcogenide channels are appealing candidates for post-silicon electronics.Based on the Boltzmann transport theory,here we report a comprehensive theoretical survey on the performance limits for monolayer MoS_(2)transistors with three prototypical gate dielectrics(Al_(2)O_(3),HfO_(2)and BN),by including primary extrinsic charge scattering mechanisms present in practical devices.A concept of"dead space"between the dielectrics and channels is proposed and used in calculation to ameliorate the general overestimation in scattering intensity of surface optical phonons,which enables an accurate description of electronic transport behavior.Crucial device indices,including charge mobility and current density,are thoroughly analyzed for transistors at post-silicon technological nodes beyond 1 nm.The on-state current is estimated to be generally greater than 2 mAμm^(-1)at channel lengths below 10 nm.The results clarify the potential benefits in performance from extremely miniaturized monolayer-channel transistors for More-Moore electronics.