摘要
针对具有立体结构的绝缘体上硅鳍式场效应晶体管(SOI FinFET),研究了表面淀积50 nm张应力SiN薄膜后SOI FinFET器件的电学特性,并对关键电学参数,如开态电流I_(on)、电流开关比I_(on)/I_(off)、跨导g_(m)、漏致势垒降低V_(DIBL)和亚阈值摆幅S_(ss)等,进行了深入分析。研究结果表明,应变对栅长较小器件的I_(on)和S_(ss)有更明显的改善,随着张应力的引入使g_(m)提升,从而显著提高了器件的I_(on),且I_(on)/I_(off)较引入前有着2个量级的提升。而g_(m)的提升归结于张应力引入而导致SOI FinFET沟道载流子迁移率的提升。V_(DIBL)和S_(ss)的改善,表明张应力的引入使器件的栅控能力显著提高。
In this paper,the FinFET device is prepared based on SOI substrate.The electrical characteristics of the SOI FinFET device after surface deposition of silicon nitride film with 50 nm tensile stress are studied.Some vital parameters,such as open current I_(on),current switching ratio(I_(on)/I_(off)),transconductance(g_(m)),drain induced barrier lowering(V_(DIBL)),and subthreshold swing(S_(ss)),etc,are analyzed.It is found that the strain has more obvious improvement on I_(on)and S_(ss)of MOS devices with short gate length.The introduction of tensile stress increases g_(m)so that I_(on)of the device is improved significantly,and the I_(on)/I_(off)rises by two orders of magnitude.In addition,the increase of g_(m)can be attributed to the increase of carrier mobility in SOI FinFET channel caused by the introduction of stress.The improvement of V_(DIBL)and S_(ss)indicates that the gate control ability of the device is improved significantly by the introduction of stress.
作者
王一杰
张静
林鸿霄
李梦达
徐步青
RADAMSON H H
闫江
WANG Yijie;ZHANG Jing;LIN Hongxiao;LI Mengda;XU Buqing;RADAMSON H H;YAN Jiang(School of Information Science and Technology,North China University of Technology,Beijing 100144,China;Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China)
出处
《现代应用物理》
2023年第3期249-256,共8页
Modern Applied Physics
基金
北京市教委基金委联合基金资助项目(KZ202210009014)。