大尺寸高端显示器件用薄膜晶体管Al–Mo复合电极坡度的形成过程与可控调节

Formation process and adjustment of the profile angle of Al–Mocomposite electrodes in thin-film transistors for large-size premiumdisplays

栅极坡度角(PA)对薄膜晶体管(TFT)性能和良率具有重要影响,如何将坡度角调节到合适的范围是TFT量产中关键技术之一.本文以大尺寸高端显示器件用a-Si TFT的Al/Mo、Mo/Al/Mo电极在磷酸系溶液下刻蚀得到的坡度角为研究对象,探究了膜层结构、Mo厚度、刻蚀时间对坡度角的影响.结果表明:在Al/Mo结构中,随着顶Mo厚度增加,Al与光刻胶之间的间隙增加,刻蚀液更易侵入,侧向刻蚀增强,坡度角减小;在Mo/Al/Mo三层电极结构中,随着底Mo厚度增加,底Mo和中间临近的Al侧壁发生电偶腐蚀,Al侧壁上形成氧化物钝化层,Al刻蚀速率减慢,坡度角变小.水池效应将导致刻蚀液残留在电极底部,阻碍新鲜刻蚀液与底部接触,底部刻蚀速率低于顶部;故当刻蚀时间延长时,底部和顶部刻蚀速率差进一步增大,导致坡度角减小.得到了Mo/Al/Mo坡度角与顶Mo和底Mo厚度回归方程,为调节坡度角和优选Mo厚度提供了依据.此电极坡度角的调节技术可为确保TFT的良率和性能提供参考.

The profile angle(PA)of gate electrodes has a significant impact on thin film transistor(TFT)performance and yield.The influence of film structure,Mo thickness,and etching time on the PAs of Al/Mo and Mo/Al/Mo electrodes of a-Si TFT etched in phosphoric-based acid solution was investigated.The results showed that in the Al/Mo dual-layer structure,the PAs decrease with the increase of the thickness of the top Mo layer,owing to the enhanced lateral etching caused by the easier invasion of the etching solution as the gap between Al and photoresist(PR)increases.In the Mo/Al/Mo three-layer electrode structure,as the thickness of the bottom Mo increases,the galvanic corrosion occurs between the bottom Mo and the adjacent middle Al sidewalls.An oxide passivation layer is formed on the Al sidewalls,which slows down the etching of Al and reduces the PAs.Due to the pool effect,the residual etchant at the bottom of the electrode hinders the contact between the fresh etchant and the bottom metal,resulting in a lower etching rate at the bottom than that at the top;thus as the etching time is extended,the difference in the etching rate between the bottom and top further increases,leading to a decrease of PAs.The regression equation between PA and the thickness of top and bottom Mo layers was obtained,providing a basis for adjusting PAs and optimizing Mo thickness.The proposed adjustment technology of electrode PAs may provide a reference for ensuring the yield and performance of TFTs.