大面阵碲镉汞芯片的耦合热应力模型与结构优化

Coupled Thermal Stress Model and Structural Optimization of Large Area Array Mercury Cadmium Telluride Chips

针对大面阵碲镉汞芯片热应力仿真分析过程中计算量与准确性不能兼容的问题,通过在芯片互联区的不同位置引入小规模铟柱阵列建立了耦合热应力的优化仿真模型。借助此模型进行热应力分析,发现在铟柱的上下表面附近区域产生了较大的热应力,同时边缘及角落处的阵列单元内部所产生的热应力更大(最高达225.69 MPa)。进一步对芯片的结构进行了优化,获得了最优读出电路及碲锌镉衬底厚度。此外,仿真结果表明,单面铟是热应力较低的铟柱结构,减小铟柱的半径可以进一步减小其内部的热应力。所提出的热应力仿真优化模型为大面阵碲镉汞芯片内部的热应力分析提供了更准确有效的分析方法以及器件设计方面的理论指导。

Aiming at the problem that the calculation quantity and accuracy are incompatible during the thermal stress simulation analysis of large area array mercury cadmium telluride chips, an optimization simulation model for coupled thermal stress is established by introducing small-scale indium column arrays at different positions in the interconnection area of the chip. Thermal stress analysis using this model shows that significant thermal stress is generated near the upper and lower surfaces of the indium column, while greater thermal stress is generated inside the array element at the edges and corners,up to 225.69 MPa. Furthermore, the structure of the chip is optimized to obtain the optimal readout circuit and zinc-cadmium tellurium substrate thickness. In addition, the simulation results show that single-sided indium is an indium column structure with low thermal stress, and reducing the radius of the indium column can further reduce its internal thermal stress. The proposed thermal stress simulation optimization model provides a more accurate and effective analysis method and device design′s theoretical guidance for the thermal stress analysis of large area array mercury cadmium telluride chips.