基于FPGA智能网卡的高性能DPDK驱动设计

Design of High-performance DPDK Driver Based on FPGA SmartNIC

FPGA智能网卡由于其硬件可编程和高吞吐等特性,被广泛的用于网络功能卸载和硬件加速。其作为一种PCIe端点设备,FPGA智能网卡一般通过操作系统驱动程序连接上层应用。然而,目前通用的内核驱动方案存在诸多性能限制,导致FPGA加速处理后的数据包不能被高效的送达应用程序。而其他已有内核旁路解决方案主要针对扩展性和吞吐性能要求较低的FPGA平台开发。面向高性能、高灵活性的网络应用场景,本文提出了一种支持FPGA智能网卡虚拟化I/O传输的多队列DPDK轮询模式驱动程序。该设计提供了在用户空间进行FPGA虚拟端口初始化和对可扩展多队列配置的操作函数功能,并提供了支持轮询模式收发的零拷贝数据传输策略。该设计实现了FPGA和应用程序之间90 Gbit/s的高性能数据收发,并能够提供具有稳定时延的网络通信服务。

Due to its hardware programmable and high throughput characteristics,FPGA SmartNIC are widely used for network protocol offloading and hardware acceleration.As a PCIe endpoint device,FPGA SmartNIC generally connect to upper-layer applications through operating system drivers.However,there are many performance limitations in the current common kernel driver solutions,so that the data packets processed by FPGA acceleration cannot be efficiently delivered to the application program.On the other hand,other existing kernel bypass solutions are mainly developed for FPGA platforms with lower requirements on scalability and throughput performance.Aiming at high-performance and high-flexibility network application scenarios,this paper proposes a multi-queue DPDK polling mode driver that supports FPGA SmartNIC virtualized I/O transmission.The design provides FPGA virtual port initialization and operation functions for scalable multi-queue configuration in user space,and provides a zero-copy data transmission strategy that supports polling mode sending and receiving.Moreover,the design realizes 90Gbit/s high-performance data transmission and reception between FPGA and application program,and can provide network communication service with stable time delay.