基于比特自检SR-Latch PUF与纠偏算法的密钥生成

Key generator design based on bits self-testing SR-Latch PUF with debiasing algorithm

首先提出了一种动态自检SR-Latch PUF(SR锁存物理不可克隆函数)结构,在SR-Latch PUF中引入PDL附加延迟线来检测SR-Latch PUF单元内部信号偏差的大小,从而检测并标记出可靠的PUF单元;其次提出了一种基于可靠性置信信息的去偏算法,将不可靠的PUF单元引入经典冯诺依曼算法的去偏过程中,改善PUF响应的偏置特性并提升了PUF的利用率;最后综合利用可靠性动态自检SR-Latch PUF、去偏算法设计了一个密钥产生电路.FPGA验证结果表明:与现有技术相比,本方案中密钥生成的错误率可以达到1×10-9,硬件开销降低了约30%.提出的去偏算法比现有算法的PUF利用率提升了32%,通过消除辅助数据的熵泄露提升了密钥的整体安全性.

A dynamic self-checking SR-Latch physically unclonable function(PUF)structure was first proposed,which introduced a PDL additional delay line in the SR-Latch PUF to detect the magnitude of signal deviation inside the SR-Latch PUF cell,so as to detect and mark the reliable PUF cells.Secondly,a de-biasing algorithm based on reliability confidence information was proposed to introduce unreliable PUF units into the de-biasing process of the classical von Neumann algorithm,which improved the bias characteristics of PUF responses and enhances the utilization of PUFs.Finally,a key generation circuit was designed using a combination of the reliable dynamic self-test SR-Latch PUF and the debiasing algorithm.FPGA verification results show that the error rate of key generation in this scheme can reach 1×10-9 and the hardware overhead is reduced by about 30%compared with the existing techniques.The proposed debiasing algorithm improves the PUF utilization by 32%over the existing algorithms and enhances the overall security of the key by eliminating the entropy leakage of the auxiliary data.