一种25Gbit/s CMOS判决反馈均衡器设计

Design of a 25 Gbit/s CMOS Decision Feedback Equalizer

为满足高速光通信系统的应用,基于标准40 nm CMOS工艺设计了一款25 Gbit/s判决反馈均衡器(DFE)电路,采用半速率结构以降低反馈路径的时序要求。主体电路由加法器、D触发器、多路复用器和缓冲器组成,为了满足25 Gbit/s高速信号的工作需求,采用电流模逻辑(CML)进行设计。经过版图设计和工艺角后仿验证,该DFE实现了在25 Gbit/s的速率下可靠工作,能提供10 dB的均衡增益,峰-峰差分输出电压摆幅约为950 mV,眼图的垂直和水平张开度均大于0.9 UI,输出抖动小于3 ps,在1.1 V的电源电压下功耗为12.5 mW,芯片版图的面积为0.633 mm×0.449 mm。

To meet the application requirements of high-speed optical communication systems,a 25 Gbit/s decision feedback equalizer(DFE) circuit was designed based on standard 40 nm CMOS technology.The circuit adopted a half-rate structure to reduce the timing requirements of the feedback path.The main circuit was composed of adder,D flip-flop,multiplexer and buffer,and was designed using current mode logic(CML) to meet the requirements of 25 Gbit/s high-speed signals.After layout design and process corner post simulation verification,the DFE operates reliably at a rate of 25 Gbit/s,providing equalization gain of 10 dB,a peak-to-peak differential output voltage swing of approximately 950 mV,and an eye diagram vertical and horizontal opening both greater than 0.9 UI.The output jitter is less than 3 ps,and the power consumption is 12.5 mW at a supply voltage of 1.1 V.The layout area of the chip is 0.633 mm×0.449 mm.