一种用于高性能FPGA的多电平标准I/O电路

A Multi-Level Standard I/O Circuit for High-Performance FPGA

为了满足等效系统门数为亿门级现场可编程门阵列(FPGA)的高速率、大吞吐量的数据传输需求,设计了一种用于高性能FPGA的多电平标准I/O电路,输入信号范围为0~2.5 V,单个差分对I/O电路的最高数据传输速率为1.25 Gbit/s。在输入缓冲器中,通过互补自偏置的折叠式放大器和施密特触发器的设计,实现了对单端输入信号、半差分输入信号和全差分输入信号等多种电平标准的兼容。在输出缓冲器中,支持多种驱动电流的输出,并且可设置输出的翻转率,降低了同步开关输出可能引起的噪声。低电压差分信号驱动器采用了预加重电流技术,提高了信号的质量。该I/O电路同时集成了数控阻抗电路,可以实时地精确匹配传输线的阻抗特性,提高了信号的完整性。仿真和实测结果表明,该支持多电平标准的I/O电路能够为高性能FPGA提供灵活、可靠的高速数据传输功能。

In order to meet the data transmission requirements of high rate and large throughput of the field programmable gate array(FPGA)with the equivalent system gate count of 100 million,a multi-level standard I/O circuit for high-performance FPGA was designed.The input signal range is from 0 V to 2.5 V,and the maximum data transmission rate of a single differential pair I/O circuit is 1.25 Gbit/s.In the input buffer,through the design of the folding amplifier with complementary selfbias and Schmidt trigger,the compatibility of multi-level standard such as single port input signal,semidifferential input signal and fully differential input signal was realized.In the output buffer,the output of multiple driving currents was supported,and the output slew rate can be set to reduce the noise that may be caused by simultaneously switching output.The low voltage differential signal driver used a preemphasis current technique to improve the quality of the signal.The I/O circuit also integrated the digitally controlled impedance circuit,which can accurately match the impedance characteristics of the transmission line in real time and improve the signal integrity.The simulation and measurement results show that the I/O circuit supporting multi-level standard can provide flexible and reliable high-speed data transmission functions for high-performance FPGA.