一种用于SAR-ADC的低失调低功耗动态比较器

A Low-Offset Low-Power Dynamic Comparator Applied for SAR-ADC

提出一种应用于SAR-ADC的低失调低功耗动态比较器。对传统双尾动态比较器的预放大器和动态锁存器两个模块进行改进,在预放大器中加入交叉耦合对管以提高增益,提升比较器精度,同时防止关键信号节点完全放电至地,实现电荷再利用以降低功耗;在动态锁存器中将PMOS单尾电流管替换为一对NMOS晶体管,双支路上各减少消耗一个阈值电压;此外,双支路之间跨接PMOS晶体管,加快尾电流对管的源极电位复位,同时减小失调,提高了比较器精度。采用SMIC 0.18μm/1.8 V CMOS工艺完成所提出动态比较器的设计和仿真验证,结果表明:在时钟频率为249 MHz,输入正弦信号ΔV_(IN)=10mV的条件下,最大失调电压为0.14 mV,功耗为19.17μW,延迟为418 ps。以上指标证明所提出的动态比较器电路在失调、功耗和速度特性上具有明显优势。

A low-offset and low-power dynamic comparator used for SAR-ADC is proposed,which improves pre-amplifier and dynamic latch,two core modules that consist of a traditional dual-tail dynamic comparator.Firstly,in pre-amplifier,the gain feature is improved by adding a cross-coupling pair of NMOS transistors,so that the comparator has higher precision,and the power consumption is reduced as well by charge-reuse technique of preventing the internal nodes from being completely discharged to the ground.Secondly,in dynamic latch,the tail current PMOS transistor is replaced by a pair of NMOS transistors to further reduce power consumption,and a PMOS transistor is short-connected between two current edges to speed up the reset of the source potential of two tail transistors,so that the power consumption can be reduced,while the realized small offset can achieve the purpose of improving comparator accuracy.By adopting SMIC 0.18μm/1.8 V CMOS process,the proposed dynamic comparator circuit is implemented and verified based on performance simulation.The simulation results show that,with 1.8V power supply voltage,249 MHz of input clock frequency,and the input sinusoidal signal of ΔV_(IN) being 10 mV,the maximum offset voltage is 0.14 mV,and the power consumption is 19.17μW with delay time of 418 ps.It is proved that the proposed comparator has the significant advantages in terms of offset voltage and power feature,while the circuit topology is simple and easy to implement.