超低导通电阻沟槽栅LDMOS器件研究

Research on Ultra-Low On-Resistance Trench Gate LDMOS Device

本文提出了一种具有超低特征导通电阻的沟槽栅横向双扩散场效应晶体管(Trench Gate Lateral Double-diffused MOSFET,TG-LDMOS).本结构源极和漏极都在表面,与BCD(Bipolar CMOS DMOS)工艺相兼容.通过引入介质沟槽、垂直栅极、栅极下方的源极多晶硅以及栅极右侧的厚氧化层,将传统集成型功率器件的一维耐压拓宽为二维耐压,包括横向耐压与纵向耐压两个方向.其中,纵向耐压不占用横向元胞尺寸,进而在相同耐压水平上,使TG-LDMOS具有分立功率器件耐压效率高、导通电阻低的特点.本结构通过仿真优化做到了击穿电压(VB)为52 V,特征导通电阻(Ron,sp)为10 mΩ·mm^(2).结果表明,TG-LDMOS突破了硅器件的极限关系,与硅极限相比特征导通电阻降低了48%.

A trench gate lateral double-diffused MOSFET(TG-LDMOS)with ultra-low specific on-resistance(Ron,sp)is proposed.With source and drain contact placement at the top silicon surface,our device is compatible with BCD(Bipo⁃lar CMOS DMOS)technologies.Compared with conventional integrated power devices,by introducing the dielectric trench,vertical gate,polysilicon source and thick oxide layer,one-dimensional withstand voltage is broadened to two-di⁃mensional withstand voltage,including both lateral and vertical directions.The vertical withstand voltage doesn't occupy the lateral cell pitch,just like the discrete power devices,so that our device has the characteristics of high voltage withstand efficiency and low on-resistance at the same breakdown voltage(VB).The TG-LDMOS is optimized to achieve VB of 52 V and Ron,sp of 10 mΩ·mm2.The simulation results show that the TG-LDMOS breaks through the silicon limit,and Ron,sp is re⁃duced by 48%compared with the silicon limit.