基于留数定理的VSC锁相环频率估计算法研究

Research on PLL Frequency Estimation Algorithm of VSC Based on Residue Theorem

在柔性直流输电系统中,锁相环对控制电压源型换流器(VSC)的电压和功率稳定具有重要作用。针对连接弱交流系统下VSC锁相环性能恶化和稳定性差的缺点,提出了一种基于留数定理的VSC锁相环频率估计算法,该算法利用留数定理,将交流电压信号由时域转换为复变域,通过求解电压复变函数的闭合路径积分对频率进行估计,实现了三相平衡和不平衡情况下交流电网频率的精确估计和快速追踪,具有良好的暂态特性和稳定性。以一个单端VSC系统为例,仿真结果验证了该算法的有效性和正确性。

In VSC-HVDC,phase locked loop(PLL)plays an important role in controlling the voltage and power stability of voltage source converter(VSC).In view of the deterioration of performance and instability of PLL interfaced with weak AC system,a PLL frequency estimation algorithm of VSC based on residue theorem is proposed in this paper.The algorithm uses residue theorem to convert AC voltage signal from time domain to complex variable domain,and the frequency estimation value is obtained by solving the closed path integral of voltage complex variable function,which realizes the accurate estimation and fast tracking of AC grid frequency under three-phase balance and imbalance conditions.This algorithm has better transient characteristics and stability.Taking a single terminal VSC system as an example,the simulation results verify the effectiveness and correctness of the algorithm.