基于电路和版图辅助的集成电路失效定位研究

Study on Schematic and Layout Assisted Fault Localization Techniques of ICs

EMMI和OBIRCH是通用的集成电路失效定位方法,二者属于器件级定位,能够将失效缩小至局部,但可能无法精确定位失效结构。在EMMI或者OBIRCH技术基础上,提出一种基于电路原理/仿真、版图、微探针测试等来辅助电路分析的定位方法。首先通过有效电激励进行EMMI和OBIRCH分析,确认标记点是否属于失效的功能电路;再通过电路原理分析或版图确定可能的漏电位置和结构,最后经电路仿真或微探针测试等方法确定精确失效点。案例研究结果显示,基于电路和版图辅助法,可快速定位氧化层击穿形成的漏电、金属划伤引起的CMOS反相器负载低阻和金属刻蚀缺陷导致的功能失效,提高了失效分析的成功率。

EMMI and OBIRCH are general failure localization methods,both methods are device level failure localization,which can only narrow down the failures to a small area,probably not precise enough to find the exact failed structure.Base on the techniques of EMMI and OBIRCH,a new approach for failure localization is proposed that involves schematic study/simulations,layout analysis and microprobe test to assist electrical analysis.Firstly,EMMI and OBIRCH should be performed under efficient electrical excitation to confirm whether marked points belong to the functional circuit that has failed.Then schematic analysis or layout study was performed to determine the potential leakage area or structure.With the assistance of schematic simulation,microprobe test and etc.,the exact failure location is traced.The results of case study demonstrate leakage current induced by oxide breakdown,low load resistance failure of CMOS inverter caused by metal scratches,and functional failures caused by metal etching defects can be quickly localized by schematic and layout assisted method,improving the success rate of failure analysis.