一种基于40nm CMOS体硅工艺的抗单粒子翻转触发器设计

Design of Single-event Upset Self-recovery Flip-flop in 40nm CMOS Technology

随着集成电路尺寸的不断减小,触发器受到单粒子打击时,电荷共享效应会使触发器电路的多个节点同时翻转.基于此,提出了一种新的触发器结构,即Rectangle DFF,可以有效过滤输入上的单粒子瞬态、并对三节点翻转免疫.该触发器由时钟晶体管堆栈架构和一个抗三节点翻转的锁存器组成,锁存器部分由12个交叉耦合的反相器和3个二输入的C单元结构组成.通过时钟晶体管堆栈结构可以屏蔽单粒子瞬态,由于3个C单元的输入不会同时翻转,能够有效屏蔽电路中的软错误.在40nm CMOS体硅工艺下的SPECTRE仿真表明,与基准的三模冗余触发器相比,面积开销降低15%,延迟降低44%,功率延迟积降低2%.

With technology scaling to the deep nanoscale level,when the filp-flop is hit by a single particle,multi-node upset due to charge sharing in the circuit.This paper proposed a novel filp-flop,namely Rectangle DFF.The flip-flop consists of a clocked transistor stack and a triple-node upset tolerant latch.Specifically,the latch part is mainly constructed from 12 cross-coupled inverters and three 2-input C-elements.Since the inputs of the C-element cannot be simultaneously,soft errors of the internal nodes can be blocked successfully.At the same time,the proposed filp-flop power consumption can be effectively reduced through a clocked transistor stack and low power delay element.In 40nm CMOS technology,extensive SPECTRE simulation results demonstrate that compared with the benchmark Flip-flop(TMR DFF),the proposed Flip-flop has an area reduction of 15%,an average delay reduction of 44%,and an average power delay product reduction of 2%.