一种基于RISC-V架构的高性能嵌入式处理器设计

Design of Embedded High-performance Processor Based on RISC-V

开源指令集RISC-V为物联网和嵌入式领域的处理器提供了强大的动力,本文针对一些具有高性能、小面积、低功耗需求的场景,设计了一种基于RISC-V指令集架构的高性能嵌入式处理器核.处理器核的代号为FRV232,采用单取指,单发射,乱序执行技术,支持RV32I基础指令集和M扩展指令集,以较低的面积实现了较高的性能.本文开发了专门用于验证FRV232核心的功能模型,功能验证阶段使用验证软件Modelsim和功能模型对处理器核心进行了完整的验证,并利用该处理器核心在FPGA上实现了基础的原型系统,使用Vivado统计了该处理器核所需的芯片面积.经过测试,FRV232在FPGA上能够稳定运行在100MHz,在该主频下,Dhrystone的性能跑分可以达到1.73DMPS/MHz.

The open-source Instruction Set Architecture(ISA),RISC-V provides power support for processor design in the Internet of Thing(IoT)and Embedded system fields in recent years.In this paper,we present the FRV232,a high-performance RISC-V based processor design.The FRV32 takes high-performance,low-power and little circuit area overhead into consideration.Meanwhile,it makes use of a variety of advanced design techniques,including single instruction fetch,single instruction issue,and out-of-order execution.This design delivers higher performance while consuming less area overhead,and it supports the standard RISC-V extensions"RV32I"(Base Integer Instruction Set-32-bit)and"M"(Integer Multiplication and Division).We realize a FPGA prototype on Xilinx Vivado development board and utilize Modelsim to verify the processor core based on the function and behavior model.The proposed prototype does not introduce timing violations when tested at 100 MHz.The benchmark Dhrystone can run at 1.73DMPS/MHz at the same frequency.